PCIE LINK SPEED in PCIE Configuration space
| Offset | Description |
| 0x06 | BIT4=1 Support Capability |
| 0x34 | Point to Capability Struct |
1.12 PCI Code and ID Assignment Specification Revision 1.12
Check PCIe SPEC for more infomation
| Capability Struct | |
| Offset | Description |
| 0x00 | CapabilityID 0x01 = PCI_CAP_ID_PMI 0x02 = PCI_CAP_ID_AGP 0x03 = PCI_CAP_ID_VPD 0x04 = PCI_CAP_ID_SLOTID 0x05 = PCI_CAP_ID_MSI 0x06 = PCI_CAP_ID_HOTSWAP 0x07 = PCI_CAP_ID_PCIX 0x10 = PCI_CAP_ID_PCIEXP 0x0C = PCI_CAP_ID_HOTPLUG |
| 0x01 | NextCapabilityStruct |
| 7.5.3 PCI Express Capability Structure | ||
| Offset | Width | Description |
| 0x02 | 16bit | PCIE Capability [3:0] Capability Version 1 – Capability Version 1 Support 2 – Capability Version 2 Support [7:4] Device/Port Type For Type 00h PCI Configuration Space header are: 0000b PCI Express Endpoint 0001b Legacy PCI Express Endpoint 1001b RCiEP 1010b Root Complex Event Collector For Type 01h PCI Configuration Space header are: 0100b Root Port of PCI Express Root Complex 0101b Upstream Port of PCI Express Switch 0110b Downstream Port of PCI Express Switch 0111b PCI Express to PCI/PCI-X Bridge 1000b PCI/PCI-X to PCI Express Bridge |
| 0x04 | 32bit | Device Capability [2:0] Max_Payload_Size SupportedDefined encodings are: 000b 128 bytes max payload size 001b 256 bytes max payload size 010b 512 bytes max payload size 011b 1024 bytes max payload size 100b 2048 bytes max payload size 101b 4096 bytes max payload size |
| 0x0C | 32bit | Link Capability [3:0] Max Link Speed (RO) 0001b Supported Link Speeds Vector field bit 0 0010b Supported Link Speeds Vector field bit 1 0011b Supported Link Speeds Vector field bit 2 0100b Supported Link Speeds Vector field bit 3 0101b Supported Link Speeds Vector field bit 4 0110b Supported Link Speeds Vector field bit 5 0111b Supported Link Speeds Vector field bit 6 [9:4] Maximum Link Width (RO) 000000b Reserved 000001b x1 000010b x2 000100b x4 001000b x8 001100b x12 010000b x16 100000b x32 [11:10] Active State Power Management (ASPM) Support 00b:No ASPM Support 01b:L0s Supported 10b:Supported 11b:L0s and L1 Supported |
| 0x10 | 16bit | Link Control [1:0] ASPM 00 Disabled 01 L0s Entry Enabled 10 L1 Entry Enabled 01 L0s Entry Enabled 11 L0s and L1 Entry Enabled [4] Link Disabled [5] Retrain Link |
| 0x12 | 16bit | Link Status Register [3:0] Current Link Speed 0001b Supported Link Speeds Vector field bit 0 0010b Supported Link Speeds Vector field bit 1 0011b Supported Link Speeds Vector field bit 2 0100b Supported Link Speeds Vector field bit 3 0101b Supported Link Speeds Vector field bit 4 0110b Supported Link Speeds Vector field bit 5 0111b Supported Link Speeds Vector field bit 6 [9:4] Negotiated Link Width 00 0001b x1 00 0010b x2 00 0100b x4 00 1000b x8 00 1100b x12 01 0000b x16 10 0000b x32 |
| 0x14 | 32bit | Slot Capabilities Register |
| 0x1A | 16bit | Slot Status Register  |
| 0x24 | 32bit | Device Capability 2 |
| 0x28 | 16bit | Device Control 2 |
| 0x2C | 32bit | Link Capability 2 [7:1] Supportd Link Speeds Vector Bit definitions within this field are: Bit 0 2.5 GT/s Bit 1 5.0 GT/s Bit 2 8.0 GT/s Bits 6:3 RsvdP |
| 0x30 | 32bit | Link Control 2 [3:0] Target Link Speed Defined encodings are: 0001b Supported Link Speeds Vector field bit 0 0010b Supported Link Speeds Vector field bit 1 0011b Supported Link Speeds Vector field bit 2 0100b Supported Link Speeds Vector field bit 3 0101b Supported Link Speeds Vector field bit 4 0110b Supported Link Speeds Vector field bit 5 0111b Supported Link Speeds Vector field bit 6 |
Offset 0x0C : 0x43 Max supported setting => Gen3 by 4
Maximum Link Width = 0x4, Max Link Speed = 0x3
Offset 0x12 : 0x43 Currently : Gen3 by 4
Negotiated Link Width = 0x4, Current Link Speed = 0x3
Offset 0x1A Bit6 Present Status
Offset 0x30 : 0x03 Target Link Speed
To re-train the device speed
1. Set offset 0x30 "Target Link speed" to the target speed value
2. Set offset 0x10 => its <value | 0x10> (e.g. 0x40=> 0x50) to disable the link
3. Set offset 0x10 => its <value | 0x20> (e.g. 0x40=> 0x60) to retrain
if it failed to adjust the Gen speed @ the device try to modify it @ its root port.
About Offset 0x10 : [5] Retrain Link
Avoiding Race Conditions When Using the Retrain Link Bit
When software changes Link control parameters and writes a 1b to the Retrain Link bit in order to initiate Link training using the new parameter settings, special care is required in order to avoid certain race conditions. At any instant the LTSSM may transition to the Recovery or Configuration state due to normal Link activity, without software awareness. If the LTSSM is already in Recovery or Configuration when software writes updated parameters to the Link Control register, as well as a 1b, to the Retrain Link bit, the LTSSM might not use the updated parameter settings with the current Link training, and the current Link training might not achieve the results that software intended.
To avoid this potential race condition, it is highly recommended that software use the following algorithm or something similar:
1. Software sets the relevant Link control parameters to the desired settings without writing a 1b to the Retrain Link bit.
2. Software polls the Link Training bit in the Link Status register until the value returned is 0b.
3. Software writes a 1b to the Retrain Link bit without changing any other fields in the Link Control register.
The above algorithm guarantees that Link training will be based on the Link control parameter settings that software intends.
沒有留言:
張貼留言