ASPM

http://www.mem.com.tw/article_content.asp?sn=0701020591
L0 – All PCI Express transactions and other operations are enabled.
L0s – A low resume latency, energy saving “standby” state.
L1 – Higher latency, lower power “standby” state. (optional)
L2/L3 Ready – Staging point for L2 or L3
L2 – Auxiliary powered Link deep energy saving state.
L3 – Link Off state. Zero power state.
LDn – A transitional Link Down pseudo-state prior to L0

ASPM control register 是存在PCIE Link Control Register。至於如何找到Link Control Register。
1.先找到PCIE Capability List Pointer Register ，而此Register 存在PCI Congfiguration Registers Offset 0x34

2.檢查Capability ID ( (1st byte))是否為0x10，如果不是，讀取Next Capability Pointer Register (2nd byte ),讀取下一個Capability.


2.檢查Capability ID (1^st byte)是否為0x10，如果不是，讀取Next Capability Pointer Register (2^nd byte ,讀取下一個Capability.